The present disclosure relates to improvement in a phase adjustment circuit that generates a phase-adjusted clock having a predetermined phase difference from a phase reference clock, which may be an input clock, etc. used as the reference for phase adjustment, and outputs the phase-adjusted clock.
In general, as one of the simplest techniques for generating a clock having a duty cycle of 50%, known is a technique where a clock having a frequency twice as high as the frequency of a clock for which the duty cycle of 50% is necessary is generated and then the frequency of the double-frequency clock is divided by a ½ frequency division circuit to obtain a 50% duty-cycle clock.
The output clock of the ½ frequency division circuit has two phase states different by 180° from each other depending on the initial state of the ½ frequency division circuit. Therefore, when the above technique is applied to a phase adjustment circuit that generates a phase-adjusted clock having a predetermined phase difference from a phase reference clock, the phase of the clock output from the ½ frequency division circuit will be in either one of the two states depending on the initial state of the ½ frequency division circuit and thus be uncertain with respect to the phase reference clock. As a result, the phase difference of the phase-adjusted clock from the phase reference clock may possibly change by 180° every time the phase adjustment circuit starts up. Note that, when a clock having a frequency twice as high as the phase reference clock is generated, the clock has rising edges at dual phase positions with respect to the phase reference clock. Therefore, even if the initial state of the ½ frequency division circuit is fixed by reset control, etc., the output phase of the 1/2 frequency division circuit with respect to the phase reference clock will vary depending on which one of the rising edges at the two phase positions is input first.
To solve the above problem that the output phase of the ½ frequency division circuit is uncertain with respect to the phase reference clock, phase comparison is conventionally performed between the output clock of the ½ frequency division circuit and the phase reference clock, and the output phase of the ½ frequency division circuit is inverted if the phase comparison result is not in a desired phase relationship, whereby the phase relationship between the phase reference clock and the output clock of the ½ frequency division circuit is kept constant. The configuration of a phase adjustment circuit that generates a phase-adjusted clock having a duty cycle of 50% using the conventional technique described above will be described with reference to FIG. 10.
As shown in FIG. 10, the phase adjustment circuit that generates a 50% duty-cycle phase-adjusted clock includes: a multiphase clock-generation circuit 10 that generates multiphase clocks having a frequency twice as high as a phase reference clock 1; a selection circuit 20 that selects one of the multiphase clocks based on a phase selection signal 2 and outputs the result as a selected clock 3; a ½ frequency division circuit 50, having a phase inversion function, that divides the frequency of the selected clock 3 by two and outputs the result as a phase-adjusted clock 4; and a phase control circuit 70 that controls the output phase of the ½ frequency division circuit 50 having the phase inversion function so that the phase reference clock 1 and the phase-adjusted clock 4 are in a phase relationship based on the phase selection signal 2.
In FIG. 10, also, the ½ frequency division circuit 50 having the phase inversion function includes: a ½ frequency divider 51 that divides the frequency of the selected clock 3 by two and outputs a ½-frequency selected clock 52; an inverter 53 that generates an inverted clock of the ½-frequency selected clock 52; and a selector 54 that selects either one of the ½-frequency selected clock 52 and its inverted clock and outputs the result as the phase-adjusted clock 4.
The phase control circuit 70 includes: a phase comparator 71 that compares phases between the phase reference clock 1 and the ½-frequency selected clock 52 and determines whether the phase of the ½-frequency selected clock 52 with respect to the phase reference clock 1 is in the range of 0°-180° or in the range of 180°-360°; and a controller 72 that controls the selector 54 to select the ½-frequency selected clock 52 if the comparison result is in a phase range based on the phase selection signal 2, or otherwise select the inverted clock of the ½-frequency selected clock 52, and output the selected clock as the phase-adjusted clock 4.
The operation of the phase adjustment circuit that generates the 50% duty-cycle phase-adjusted clock 4 shown in FIG. 10 will be described. Assume herein that a four-phase clock generation circuit is used as an example of the multiphase clock-generation circuit 10.
First, the four-phase clock generation circuit 10 generates four-phase clocks having a frequency twice as high as the phase reference clock 1. The selection circuit 20 then selects one of the four-phase clocks based on the phase selection signal 2 as the selected clock 3. The four-phase clocks are clocks having phases equally spaced from each other by a quarter of a half cycle of the phase reference clock 1. By changing the phase selection signal 2, four-stage phase adjustment is possible. In FIGS. 11A and 11B, examples of the phase reference clock 1, the four-phase clocks, and the selected clock 3 obtained when clock [1] is selected among the four-phase clocks are shown.
Thereafter, the ½ frequency divider 51 divides the frequency of the selected clock 3 selected by the selection circuit 20 by two, to generate the ½-frequency selected clock 52. At this time, it is uncertain whether the phase of the ½-frequency selected clock 52 with respect to the phase reference clock 1 is in the range of 0°-180° or in the range of 180°-360°, which depends on the initial state of the ½ frequency divider 51 and the input timing of the selected clock 3. FIG. 11A shows the case where the phase of the ½-frequency selected clock 52 is in the range of 0°-180° with respect to the phase reference clock 1, and FIG. 11B shows the case where the phase of the ½-frequency selected clock 52 is in the range of 180°-360° with respect to the phase reference clock 1.
In view of the above, the phase comparator 71 of the phase control circuit 70 compares phases between the phase reference clock 1 and the ½-frequency selected clock 52 and determines whether the phase of the ½-frequency selected clock 52 with respect to the phase reference clock 1 is in the range of 0°-180° or in the range of 180°-360°. The controller 72 of the phase control circuit 70 controls the selector 54 to select the ½-frequency selected clock 52 if the comparison result is in the phase range based on the phase selection signal 2, or otherwise select the inverted clock of the ½-frequency selected clock 52.
For example, assume that the phase of the ½-frequency selected clock 52 with respect to the phase reference clock 1 is in the range of 0°-180°. In this case, the controller 72 of the phase control circuit 70 controls the selector 54 to output the ½-frequency selected clock 52 as it is (non-inverted clock) as the phase-adjusted clock 4 if the phase selection signal 2 indicates control in the range of 0°-180°, or output the inverted clock of the ½-frequency selected clock 52 as the phase-adjusted clock 4 if the phase selection signal 2 indicates control in the range of 180°-360°. FIG. 11A shows two forms of the phase-adjusted clock 4 obtained when controlled to be in the phase range of 0°-180° and in the phase range of 180°-360° in the case where the phase of the ½-frequency selected clock 52 is in the range of 0°-180° with respect to the phase reference clock 1. FIG. 11B shows two forms of the phase-adjusted clock 4 as described above in the case where the phase of the ½-frequency selected clock 52 is in the range of 180°-360° with respect to the phase reference clock 1.
With the operation of the phase control circuit 70 described above, the phase adjustment range of the phase-adjusted clock 4 with respect to the phase reference clock 1 is controlled to be in the phase range selected based on the phase selection signal 2, irrespective of the initial state of the ½ frequency divider 51 and the timing of the input clock.
In other words, the phase adjustment circuit can adopt the technique of generating a double-frequency clock and dividing the frequency of the clock by two to obtain a 50% duty-cycle clock, and yet can generate the phase-adjusted clock without being affected by the initial state of the ½ frequency division circuit and the timing of the input clock into the ½ frequency division circuit.
Note that Japanese Patent Publication No. 2000-244311 discloses, in its clock switch adjustment method, the technique of comparing phases between the output clock of the ½ frequency division circuit and the reference clock and inverting the output phase of the ½ frequency division circuit if the phase comparison result is not in a desired phase relationship, thereby controlling the output phase of the ½ frequency division circuit to be in a desired phase state.